The "Run Simulation" icon or the command Simulate -> Start Simulation both give access to the automatic extraction and analog simulation of the layout.
- Click on Voltage vs Time to obtain the transient analysis of all visible signals. The delay between the selected start node and selected stop node is computed at VDD/2. You can change the selected start node in the node list, in the right upper menu of the window. You can do the same for the selected stop node.
- Click on Voltage and Currents so as to make all voltage curves appear in the lower window, and the VDD, the VSS and the desired MOS currents appear in the upper window. In that mode, the dissipated power within the simulation is also displayed.
- Click on Voltage vs. Voltage to obtain transfer characteristics between the X-axis selected node and the Y-axis selected node. Initially the start node is the first clock or pulse of the node list, and the stop node is the first varying node. This mode is useful for the computing of the Inverter characteristics (commutation point), the DC response of the operational amplifier, or for the Schmitt trigger to see the hysteresis phenomenon. The first simulation computes the value of the stop node for start node varying from 0 to VDD. The second click on " Simulate " computes the same for start node varying from VDD to 0.
- Click on Frequency & Voltages so as to make all voltage curves appear in the lower window, and to plot the variation of the switching frequency of one selected signal. This mode is very useful for monitoring the output signal of oscillators. NOTE : You can modify the minimum simulation step D t, but it may be dangerous. If you increase D t the simulation speed improves but the numerical error may lead to unstable simulations. If you decrease D t, the simulation speed is decreased too but the numerical precision is improved. The risk of computing divergence is reduced.
Select the model you wish to use to perform simulations. By default, the MOS model is BSIM4. Add a text on the layout starting by "LEVEL1" if you wish to use permanently the MOS level1, "LEVEL3" if you wish to use permanently the MOS level31, "BSIM4" if you wish to use permanently BSIM4.
Note: previous versions of Microwind used LEVEL3 as a default model. This was changed for the shake of accuracy.
The default extraction includes the removal of redundant boxes (Purge) and the removal of overlaps (Merge). The fast extraction does not handle Purge nor Merge operations.
The MOS level can be chosen between level 1,3 and BSIM4. See the user's manual for more details about those models. Other options concern the computation of lateral capacitance and vertical crosstalk capacitance. The temperature may be changed in this screen.
The simulation is performed directly on the layout with a palette of colors. The most interesting layout files to be simulated in this mode are analog blocks such as the DAC.
Crosstalk is a parasitic effect that affects long lines routed close from each other. The proximity of the interconnects creates a coupling effect that provokes crosstalk between the affector and victims. By default, the analog simulator do not consider the crosstalk capacitance.
- Use the command "Simulate" -> "With crosstalk" to perform analog simulation including the crosstalk capacitance extraction and simulation.
- Click "Evaluate Min/max" to compute on the screen the maximum amplitude of the crosstalk
There are three types of capacitance for interconnects: capacitance to substrate body, inter-layer capacitance and lateral crosstalk capacitance. The inter-layer capacitance refers vertical coupling between layers, while lateral crosstalk capacitance refer to adjacent interconnect coupling. The crosstalk capacitance value per unit length is given in the design rule file for a predefined interconnect width (w=4l ) and spacing (d=4l ). In Microwind, the computed crosstalk capacitance is not dependant on the interconnect width w. The computed crosstalk capacitance value is proportional to 1/d where d is the distance between interconnects.
Example: The demonstration of crosstalk can be made with the circuit CrosstalkBig.MSK. The schematic diagram of the circuit corresponds to two strong inverters, and strongly coupled interconnects. We used one interconnect "victim" fixed to Vss, surrounded by two aggressors which are switching, to exhibit the crosstalk effect.
The simulation icons add properties to the nodes. Properties are applied to the electric nodes of the circuit in order to serve as simulation guides. You must specify which node is assigned to which voltage before starting the analog simulation.
VDD & VSS. The node is pushed to the power supply voltage with icon Vdd, and pulled to the ground 0V with icon Vss.
CLOCK. When a node becomes a clock, the parameters of the latter are divided as follows : rise time, level one, fall time, and level zero. All values are expressed in nan-second (ns). If you ask for a second clock, the period will be multiplied by two.
- You may alter level 0 and level 1 by entering a new value with the keyboard.
- To generate a clock starting from VDD instead of VSS, click on Invert L/H.
- Use Period * 2 to multiply the clock period by two.
- Use Period /2 to divide the clock period by two.
PULSE. The pulse switches from "Level 0" (0 by default) to "Level 1" (VDD by default" depending on the user-defined time table.
- Enter the string "0101100" and press "Insert". The time-table is updated
- Click "Erase": all lines situated after the selected element of the time-table are erased.
SINUS. The sinusoidal waveform parameters are the amplitude, the offset, frequency and phase.
VISIBLE NODE. Click on the "eye" and click on the existing text in the layout to make the chronograms of the node appear. Initially, all nodes are invisible, but the clocks and impulse nodes are subsequently made visible.
This command simulates the discharge of floating gates due to a very long exposure to ultra violet light (in practice around 20mn). As a result, all charges stored in floating polysilicon gates are discharged.
Click on the "Mos characteristics" icon situated in the main menu. The Id/Vd curve of the default MOS (W=20µm, L=L minimum) appears.
Click on the "Process View" icon or "Simulate-> Process Section in 2D" to access process simulation. A mouse-operated line is given and embodies the cross section. The screen below appears. The arrows can be used to move the cross-section to the right or to the left in the X axis, and forward and backward in the Y axis. Zooms in and out are available. Remove the layer names by removing the tick in front of "Layer infos".
Click the "3D icon" or "Simulation -> Process Steps in 3D" to see the 3-dimentionnal aspect of your circuit. Click "Next step" to watch how the layout currently edited on the screen will be fabricated using the selected technology. Use the arrow to shift the displayed portion. Zooms in and out are available.
In demo mode, the steps of the CMOS process are illustrated in sequence.
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